Many electrical circuits designed today are extremely complex and include, for example, many millions of individual circuit elements such as transistors and digital logic gates. Circuit complexity has greatly surpassed the capacity of all conventional design techniques using computer aided design systems. In particular, circuit complexity is challenging the available resources of even the largest, most sophisticated computer aided automatic layout place and route design systems.
There are primarily three paradigms by which automatic layout place and route design systems are used by engineers to design electrical circuits layout. The first is called the flat paradigm. In the flat paradigm, the circuit under design is represented entirely at a physical layout abstraction level such that individual logic gates and pre-laid-out function blocks are shown directly and are placed and routed directly by automatic layout techniques. The advantage of the flat paradigm is that to optimize the global placement of layout gates and global wiring of connections between gates is relatively easy. The disadvantage of the flat paradigm is that the requisite computer resources and computing time increase exponentially with an increase of complexity of the circuit under design and can quickly overwhelm the computer capacity of any computer aided design system and the project design schedule.
This disadvantage of the flat paradigm is overcome by the second paradigm, i.e., the hierarchical paradigm. In the hierarchical paradigm, circuit elements are combined into functional blocks such that the functional blocks serve as abstractions of underlying circuit elements. Such functional blocks can be combined into larger, more abstract, functional blocks of a higher level of a hierarchy. For example, a computer processor can be designed as including a relatively small number of functional blocks including a memory management block, an input/output block, and an arithmetic logic unit. The arithmetic logic unit can be designed to include a relatively small number of functional blocks including a register bank, an integer processing unit, and a floating point processing unit. The integer processing unit can include sub-blocks such as an adder block, a multiplier block, and a shifter block. At the lower levels of the hierarchical design specification, blocks are as simple as flip-flops and digital logic gates, and blocks are individual elements such as transistors, resistors, capacitors, inductors, and diodes at the lowest level of the hierarchy.
The primary advantage of the hierarchical paradigm is that engineers can design complex circuits by designing relatively small functional blocks and using such designed blocks to build bigger blocks. In other words, the seemingly insurmountable job of designing a highly complex circuit is divided into small, workable design projects. Each of the function blocks can be easily placed and routed by the flat paradigm. The use of computer resources and computing time can be controlled simply by this paradigm. In addition, functional blocks designed for one circuit can be used as components of a different circuit, thereby reducing redundant effort by the engineers.
The primary disadvantage of the hierarchical paradigm is that significantly accurate global net wiring is particularly difficult to realize since each functional block of a hierarchical design is independently instantiated to render a flat layout of the specific electrical elements which implement the hierarchical design. The timing delay skew of a clock net, for example, between such independently instantiated functional blocks must be minimized in a layout design, i.e., various flip-flop logic gates must receive a global clock signal in the same time. However, in the actual design, electrical signals propagate from source to various destinations at different times due to variations in specific routes and surrounding conditions. Several conventional techniques for resolving timing delay skews, e.g., the "Clock-Tree-Synthesis," require circuit designs specifying according to the flat paradigm to minimize the timing delay skew. Circuit design according to the hierarchical paradigm is generally inadequate to resolve global net routing requirements since the functional blocks have been abstracted and fixed.
The third paradigm is called the "Hybrid Paradigm" and provides the advantages of both the flat and hierarchical paradigms by which a hierarchical design can be more efficiently and accurately rendered to a layout-level circuit. This hybrid paradigm is described more completely in U.S. patent application Ser. No. 09/098,599 by Cai Zhen and Zhang Qiao Ling entitled "Hybrid Design Method and Apparatus for Computer-Aided Circuit Design" filed Jun. 17, 1998. Circuit layout design using CAD systems according to the hybrid paradigm have shown significantly better performance than systems according to either of the other two paradigms.
In both hierarchical and hybrid paradigms, circuit designs are partitioned into sub-blocks and glue logic circuits including primary logic components can not be simply partitioned into sub-blocks. The partitioned circuit is normally referred to as "top-level". Circuits that are completely included within sub-blocks are referred to as "block-level". A sub-block includes connection terminals called "pins" and internal circuit logic of the sub-block. The pins of a sub-block act as relay points that connect the sub-blocks and glue logic in the top-level and connect the internal circuitry of sub-blocks with the top-level circuits.
The location of these pins of sub-blocks are important in the hierarchical paradigm and hybrid paradigm. Good pin locations can result in an integrated-circuit layout of a smaller physical area and faster electrical signal propagation. Conversely, poor pin locations result in a bigger circuit layout area and slower signal propagation through the circuit. Hence, the pins need to be optimized in the hierarchical and hybrid paradigms.
Currently, pin optimization methods are limited to one level optimization, i.e., top-level pin optimization. There are various techniques for top-level pin optimization process. The major assumptions of these methods are: (1) all sub-blocks are ideal and (2) timing delays are uniform. The first assumption is based upon an assumption that routability inside sub-blocks is independent of pin locations. As used herein, the term routability refers to the degree to which components can be wired without design-rule violation in a given area. The second assumption is based upon an assumption that the timing delay from each pin to its connected components is the same regardless of the distance and capacitive load effects of the connected components. Thus, any pin optimization methods based on these two assumptions will result in two disadvantages: (i) sub-blocks may not be routable and (ii) timing delay from sub-block pins to components on the same net is non-predictable, perhaps resulting in very large timing delay skews of the net.
What is needed is a system for optimizing pins of sub-blocks globally with respect to both geometry locations and electrical signal timing considerations, and with respect to both top-level optimization and block-level optimization.